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I have a question regarding the Write Through cache equation which you have given in Handout 12. You haveCorrect, in a fully pipelined cache, writes will almost never stall. We will assume that they never stall, but for those who are interested in the details:T_Avg = (%Write)(T_Acc1) + ...
I don't quite understand why you associate only T_Acc1 to the writes instead of the actualy time required to write the data in the register to main memory. Is it simply due to the fact that writes never stall for write-through caches?
The only time a write will stall in a fully-pipelined Write-Through cache is when there is sufficient bus conjestion that the write-buffer fills up, preventing subsequent writes from entering the cache. The AXP-21164 has a 6 entry write-buffer where each entry contains up to 32-bytes of consecutive data.
Also, for T_Write(i), is this always 1 cycle as stated in the opening paragraph?T_Write is implementation dependent, so it's possible that some machines have a T_Write that is not 1, but it's unlikely.
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