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CPSC 418: Handout 12 : Write-Through / Write-Back Caching

General Info

In a write-back scheme, the time for a write-hit is usually one more cycle than for a read-hit. This is because a read can read the data and tag from the cache at the same time. A write has to first read the tag and check for a hit before it can write the data to the cache. This is reflected in the T_Write variable below.

T_Avg Average time to complete memory reference
%Hit(i) Percentage of references that hit at level (i)
%Miss(i) Percentage of references that miss at level (i)
T_Acc(i) Access time at level (i) (time for read, hit check)
%Write Percentage of accesses that are writes (stores)
%Read Percentage of accesses that are read (loads)
T_Write(i) Time to do a write at level (i) (only used with write-back)
T_Fill(i) Time to fill cache line at level (i)
%Dirty Percentage of cache lines that are dirty (have been modified since read into cache)

T_Avg	Average time to complete memory reference
%Hit(i)	Percentage of references that hit at level (i)
%Miss(i)	Percentage of references that miss at level (i)
T_Acc(i)	Access time at level (i) (time for read, hit check)
%Write	Percentage of accesses that are writes (stores)
%Read	Percentage of accesses that are read (loads)
T_Write(i)	Time to do a write at level (i) (only used with write-back)
T_Fill(i)	Time to fill cache line at level (i)
%Dirty	Percentage of cache lines that are dirty (have been modified since read into cache)

Write Back

T_Avg = (%Hit1)(T_Acc1 + (%Write)(T_Write1)) + (%Miss1)((%Dirty1)(T_WB1) + (T_Fill1))

Write Through

T_Avg = (%Write)(T_Acc1) + (%Read)((%Hit1)(T_Acc1) + (%Miss1)(T_Fill1))

Note: For write-through caches, writes never stall.

This is because other instructions don't need to wait for a store to complete, while a load almost always has an instruction waiting for its result.
This is a bit idealized, because there could be contention for busses, etc.

Note:Equation for write-back cache is somewhat idealized. Sometimes with write-back, we still have to write to the cache, because a previous read may have loaded a cache line. If the cache is fully pipelined, which most are these days, then this will not slow down the instruction flow through the rest of the CPU.

Example

Adapted from 1995, HW-09, prob 2 (Hennessey&Patterson prob 8.4)

Given:

Memory system with split level-1 cache (I-cache, D-cache)
T_Acc1 = 1 cycle
%Write = 45%
T_Write1 = 1 cycle
T_Fill1 = 10cycles
T_WB1 = 10 cycles (Time to write dirty cache block to memory)
%Hit_Data = 96%
%Hit_Inst = 98%
%Dirty = 50%

Instructions

Instructions are read-only and so are same for both write-back and write-through.

TA_Inst = (%Hit_Inst)(T_Acc1) + (%Miss_Inst)(T_Fill1)
TA_Inst = (0.98)(1) + (0.02)(10)
TA_Inst = 1.18

WriteBack

T_Avg_Data = (%Hit_Data)(T_Acc1 + (%Write)(T_Write1)) + (%Miss_Data)((T_Fill1) + (%Dirty)(T_WB1))
T_Avg_Data = (0.96)(1 + 0.45*1) + (0.04)((10) + (0.50)(10))
T_Avg_Data = 1.99

WriteThrough

Data
T_Avg_Data = (%Write)(T_Acc1) + (%Read)((%Hit_Data)(T_Acc1) + (%Miss_Data)(T_Fill1))
T_Avg_Data = (0.45)(1) + (0.55)((0.96)(1) + (0.04)(10))
T_Avg_Data = 1.20

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Last modified: 09 Mar 96