CPSC 418: Reading List


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Contents:
Architecture Overview | IO:    Disks and Networks | Caches | Midterm | Instruction Level Parallelism | Thread Level Parallelism |


Warning: Subject to change with notice!

This list is my current snapshot of the course reading list. I will certainly make changes as the semester progresses. I will try very hard to give at least two weeks notice on any changes. Whenever the reading list is changed, I will up-date this page (you may have to force a reload in your browser), and I will post a notice to the course newsgroup.

Architecture Overview
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Sep.   3: Course Overview
Sep.   5: " Cramming More Components onto Integrated Circuits ", Moore, Electronics, pp. 114-117, Apr. 1965; and
"The Future of Microprocessors", Yu, IEEE Micro, 16(6):46-53, 1996.
Sep. 10: "Database buffer size investigation for OLTP workloads, Tsuei, Packer, & Ko, Proceedings of SIGMOD-97, pp. 112-122, 1997; and
"Benchmarks are Bunk", Diefendorff, Microprocessor Report, vol. 14:6, June 2000, pp. 3-4, and
"The Shift from Speed to Power Dissipation", Leibson, Microprocessor Report, vol. 14:10, October 2000, pp. 3-4.
Sep. 12: "Designing and Programming the Emotion Engine", Oka and Suzuoki, IEEE Micro, vol. 19:6, Nov/Dec 1999, pp. 20-28; and
"Microsoft Weighs in with X-box", Glaskowsky, Microprocessor Report, vol. 14:4, April 2000, pp. 1,8-11.
Sep. 17: Probability review


IO:    Disks and Networks
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Disks:
Sep. 19: "An Introduction to Disk Drive Modeling", Ruemmler & Wilkes, IEEE Computer 27(3): 17-28, 1994.
Sep. 24: "A Case for Redundant Arrays of Inexpensive Disks", Patterson, Gibson, & KatzProceedings of the ACM SIGMOD Conference, Chicago, IL, Jun 1988.


Networks
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Sep. 26: "Ethernet: Distributed Packet Switching for Local Computer Networks", Metcalfe & Boggs, Communications of the ACM, 19(7):395-404.
Oct.   1: "Fast Switched Backplane for a Gigabit Switched Router", McKeown.
Oct.   3: "Efficient Randomized Algorithms for Input-Queued Switch Scheduling Shah, Giaccone, & Prabhakar.


Caches
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Oct.   8: Cache review.
Read: Introduction to chapter 6 in Readings in Computer Architecture, Hill, Jouppi, & Sohi (eds.), 2000, pp. 363-370.
Oct. 10: "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers",  Jouppi, Proceedings of the 17th Annual Symposium on Computer Architecture, Computer Architecture News, 18(2): 364-373, 1990.
Oct. 15: "Using Cache Memory to Reduce Processor-Memory Traffic", Goodman, Proceedings of the Tenth International Symposium on Computer Architecture, Stockholm, Sweden, pp. 124-131, June 1983.
Oct. 17: "The Alpha 21364 Network Architecture", Mukherjee, Bannon, Lang, Spink, & Webb, IEEE Micro, vol. 22:1, Jan/Feb. 2002, pp. 26-35.


Midterm:
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Oct. 22: Midterm exam: "My cache or yours? Making storage more exclusive", Theodore Wong & John Wilkes, Proceedings of USENIX 2002, pp. 161-175.

Instruction Level Parallelism
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Oct. 24: Introduction to instruction level parallelism:
Introduction to chapter 4 in Readings in Computer Architecture, Hill, Jouppi, & Sohi (eds.), 2000, pp. 175-183; and
and section 6.7 of Computer Architecture: A Quantitative Approach, Hennessy and Patterson, pp. 290-319.
Oct. 29: Introduction to instruction level parallelism, continued.
Oct. 31: "The MIPS R10000 Superscalar Microprocessor", Yeager.  IEEE Micro, 16(2):28-40, 1996.
Nov.   5: CLASS CANCELLED
Nov.   7: "Introducing the IA-64 Architecture", Huck, Morris, et. al., IEEE Micro vol. 20:5, Sept/Oct 2000, pp. 12-23.

Thread Level Parallelism
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Nov.   12: " Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Tullsen, Eggers, et. al, Proceedings of the 23rd Annual Symposium on Computer Architecture, pp. 191-202, May 1996.
Nov. 14: "Compaq Chooses SMT for Alpha", Diefendorff, Microprocessor Report, vol. 13:16, 6 December 1999, pp. 1,6-11, and
"Intel Embraces Multithreading", Krewell, Microprocessor Report, vol. 15:9, September 2001, pp. 1,5
Nov. 19: "The Case for a Single-Chip Multiprocessor", Olukotun, Nayfeh, et. al., In Proceedings of ASPLOS-VII, pp. 2-11, Oct. 1996.
Nov. 21: "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing", Barroso, Gharachorloo, et. al., In Proceedings of ISCA-27, pp. 282-293.

Current Topics
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Nov. 26
   -- 29:
Topics to be chosen as the term progresses. Possibilities include: quantum computing, bio-computing, nano-technology, embedded processors, high-speed circuits for pipelines and interconnect, architecture for low power, etc.

Final Exam
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Copyright 2002 Mark R. Greenstreet
mrg@cs.ubc.ca
Last Modified: 4 September 2001