Contents:
[
Architecture Overview |
Disks and Disk Arrays |
Networks |
Memory |
Binary Translation |
Exploiting Parallelism |
]
Jan. 2: Course Overview
Jan. 4: "Cramming More Components onto Integrated Circuits",
Moore, HJ&S pp. 56-59;
and "The Future of Microprocessors"
Yu, HJ&S pp. 681-688
Jan. 9: "Database Buffer Size Investigation for OLTP Workloads",
Tsuei, Packer, and Ko,
in Proceedings ACM SIGMOD 1997,
pp. 112-122; and
"RS/6000: S80 TPC-C Benchmark Analysis",
Olszewski and Romero.
Jan. 11: "Designing and Programming the Emotion Engine",
Oka and Suzuoki, IEEE Micro, vol. 19:6, Nov/Dec 1999,
pp. 20-28; and
"Microsoft Weighs in with X-box",
Glaskowsky,
Microprocessor Report, vol. 14:4,
April 2000, pp. 1,8-11.
IO: Disks and Networks
Jan. 16: "An Introduction to Disk Drive Modeling",
Ruemmler & Wilkes. In HJ&S pp. 462-473
Jan. 18: "A Case for Redundant Arrays of Inexpensive Disks",
Patterson, Gibson, & Katz. In HJ&S pp. 474-481
Jan. 23: "The HP AutoRAID Hierarchical storage system",
Wilkes, Golding, Staelin, and Sullivan,
ACM Transactions on Computer Systems, vol.14:1,
pp. 108-136, February 1996.
Networks
Jan. 25: "Ethernet: Distributed Packet Switching for Local Computer
Networks", Metcalfe & Boggs. In HJ&S pp. 482-491.
Jan. 29: "Fast Switched Backplane for a Gigabit Switched Router",
McKeown.
Feb. 1: "Intel Network Processor Targets Routers",
Halfhill, Microprocessor Report, vol. 13:12,
13 September 1999, pp. 1,6-10; and
"Agere's Pipelined Dream Chip",
Krewell, Microprocessor Report, vol. 14:6,
June 2000, pp. 34-36.
These two papers were CANCELLED.
They will not be considered for any exam or homework.
Caches
Feb. 6: Cache review.
Read: Introduction to chapter 6 in HJ&S pp. 363-369
Feb. 8: "Improving Direct-Mapped Cache Performance by the Addition
of a Small Fully-Associative Cache and Prefetch Buffers."
Jouppi. In HJ&S pp. 395-404
Feb. 13: "Using Cache Memory to Reduce Processor-Memory Traffic",
Goodman. In HJ&S pp. 387-394
Feb. 15: "Starfire: Extending the SMP Envelope",
Charlesworth, IEEE Micro, vol. 18:1, Jan/Feb. 1998,
pp. 39-49.
Feb. 20: MIDTERM BREAK: no Lecture
Feb. 22: MIDTERM BREAK: no Lecture
Feb. 27: Midterm
Binary Translation
Mar. 1: "Dynamo: A Transparent Dynamic Optimization System",
Bala, Duesterwald, and Banerjia,
in Proceedings of ACM SIGPLAN'00 Conference on
Programming Language Design and Implementation,
pp. 1-12, June 2000.
Mar. 6: "Transmeta Breaks x86 Low-Power Barrier",
Halfhill, Microprocessor Report, vol. 14:2,
Feb. 2000, pp. 1,9-18; and
"Top PC Vendors Adopt Crusoe",
Halfhill, Microprocessor Report, vol. 14:7,
July 2000, pp. 1,8-12.
Mar. 8: Guest Lecture: Cristina Cifuentes, SUN Microsystems.
Exploiting Parallelism
Mar. 13: Introduction to instruction level parallelism:
read: introduction to chapter 4 in HJ&S, pp. 175-183;
and section 6.7 of Computer Architecture:
A Quantitative Approach, Hennessy and Patterson,
pp. 290-307.
Mar. 15: Introduction to instruction level parallelism, continued.
Mar. 20: "The MIPS R10000 Superscalar Microprocessor", Yeager.
In HJ&S pp. 275-287.
Mar. 22: "Introducing the IA-64 Architecture",
Huck, Morris, et. al.,
IEEE Micro vol. 20:5, Sept/Oct 2000,
pp. 12-23.
Mar. 27: "Exploiting Choice: Instruction Fetch and Issue on
an Implementable Simultaneous Multithreading Processor",
Tullsen, Eggers, et. al, in JH&S, pp. 350-361.
Apr. 29: "Compaq Chooses SMT for Alpha",
Diefendorff, Microprocessor Report, vol. 13:16,
6 December 1999, pp. 1,6-11.
Apr. 3: "The Case for a Single-Chip Multiprocessor",
Olukotun, Nayfeh, et. al.,
In Proceedings of ASPLOS-VII, pp. 2-11,
Oct. 1996.
Apr. 5: "Piranha: A Scalable Architecture Based on Single-Chip
Multiprocessing", Barroso, Gharachorloo, et. al.,
In Proceedings of ISCA-27, pp. 282-293.
Copyright 2000 Mark R. Greenstreet
mrg@cs.ubc.ca
Last Modified: January 1, 2001