CPSC 418: Readings

This list will change as I select readings for the class!

Required Reading
Supplemental or Background Reading
Other readings

The following abbreviations are used:

ASPLOS: Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems.
ISCA: Proceedings of International Symposium on Computer Architecture .
MR: Microprocessor Report.
HP: J. L. Hennessy & D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd Edition (available in the CICSR reading room and Main Library course reserve)
HP-old: J. L. Hennessy & D. A. Patterson, Computer Architecture: A Quantitative Approach, 1st Edition
PH: D. A. Patterson & J. L. Hennessy, Computer Organization & Design: The Hardware/Software Interface (The text used in CPSC 318)

Required Reading

Articles are handed out during class -- one copy per student.

Assigned First Discussed Reading
Jan 7 Jan 14 B.Case, "SPEC95 Retires SPEC92", MR, 9, 11 (21 Aug 95).
Jan 7 Jan 14 L.Gwennap, "Intel Updates Its iCOMP Index", MR (8 July 96).
Jan 12 Jan 19 J.A.Fisher & B.R.Rau, "Instruction Level Parallel Processing", Science, 253 (13 Sept 91), 1233-1241.
Jan 12 Jan 21 J.E.Smith & G.S.Sohi, "The Microarchitecture of Superscalar Processors", Proc. of the IEEE, 83, 12 (Dec 95), 1609-1624.
Jan 19 Jan 26 J.E.Smith & A.R.Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", IEEE Trans. on Computers, 37, 5 (May 88), 562-573.
Jan 19 Feb 2 L.Gwennap, "New Algorithm Improves Branch Prediction", MR, 9, 4 (27 March 95).
Jan 26 Feb 4 G.S.Sohi & M.Frenklin "High-Bandwidth Data Memory Systems for Superscalar Processors" 53-62.
Jan 26 Feb 9 N.P.Jouppi & S.J.E.Wilton, "Tradeoffs in Two-Level On-Chip Caching", Western Research Laboratory (Digital) Research Report 93/3.
Jan 26 Feb 11 S.Przybylski "SDRAMs Ready to Enter PC Mainstream" Microprocessor Report Vol 10, No 6 (May 6, 96).
Feb 29 Mar 2 D.Bhandarkar & D.W.Clark, "Performance from Architecture: Comparing a RISC and CISC with Similar Hardware Organization", ASPLOS 4, Palo Alto (April 91), 310-319.
Feb 29 Mar 4 J.E.Smith & S.Weiss, "PowerPC 601 and Alpha 21064: A Tale of Two RISCs", IEEE Computer, 27, 6 (June 94), 46-58.
Mar 2 Mar 9 HP Appendix D or Equivalent (x86 ISA)
Mar 9 Mar 16 M.Slater, "AMD's K5 Designed to Outrun Pentium", MR, 8, 14 (24 Oct 94).
Mar 9 Mar 16 L.Gwennap, "Intel's P6 Uses Decoupled Superscalar Design", MR, 9, 2 (19 Feb 95).
Mar 9 Mar 18 B.Case "New Instruction Sets Are Comming" Microprocessor Report Vol. 10 No. 10 (Aug. 5, 96).
Mar 9 Mar 18 W-M.W.Hwu et al., "Compiler Technology for Future Microprocessors", Proc IEEE, Vol. 83 No. 12 (December 1995), 1625-1640.
Mar 18 Mar 23 L.Gwennap, "Intel, HP Make EPIC Disclosure", Microprocessor Report Vol. 11 No. 14 (Oct. 27, 97).
Mar 18 Mar 23 L.Gwennap, "Merced Slips to Mid-2000", Microprocessor Report Vol. 12 No. 8 (Jun. 22, 98).
Mar 18 Mar 23 H.McGhan & M.O'Connor, "PicoJava: A Direct Execution Engine for Java Bytecode", IEEE Computer Vol. 31 No. 10 (Oct 98), 22-30.
Mar 18 Mar 25 D.Dobberpuhl, "The Design of a High Performance Low Power Microprocessor", Intl Symp Low Power Electronic Design, 1996, 11-16.
Mar 18 Mar 30 R.F.Sproull, I.E.Sutherland, C.E. Molnar, "Counterflow Pipeline Processor Architecture", Sun Microsystems Laboratories Technical Report, SMLI TR-94-25 (April 1994).

Assigned	First Discussed	Reading	Topic
Jan 5	Jan 12-14	HP 1.1-1.8. (HP-old Ch 1 and 2 is OK.)	Industry Trends and Cost, Measuring Performance
Mar 25	Apr 1	HP Appendix A. (HP-old Appendix A is fine. PH Chapter 4 is pretty much OK, too.)	Arithmetic
Mar 30	Apr 6	HP 8.1, 8.3, 8.4	Multiprocessor Intro, Cache Coherence

CPSC 418: Readings

Required Reading

Recommended Readings

Other Readings

Assigned	First Discussed	Reading
Jan 7	Jan 14	B.Case, "SPEC95 Retires SPEC92", MR, 9, 11 (21 Aug 95).
Jan 7	Jan 14	L.Gwennap, "Intel Updates Its iCOMP Index", MR (8 July 96).
Jan 12	Jan 19	J.A.Fisher & B.R.Rau, "Instruction Level Parallel Processing", Science, 253 (13 Sept 91), 1233-1241.
Jan 12	Jan 21	J.E.Smith & G.S.Sohi, "The Microarchitecture of Superscalar Processors", Proc. of the IEEE, 83, 12 (Dec 95), 1609-1624.
Jan 19	Jan 26	J.E.Smith & A.R.Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", IEEE Trans. on Computers, 37, 5 (May 88), 562-573.
Jan 19	Feb 2	L.Gwennap, "New Algorithm Improves Branch Prediction", MR, 9, 4 (27 March 95).
Jan 26	Feb 4	G.S.Sohi & M.Frenklin "High-Bandwidth Data Memory Systems for Superscalar Processors" 53-62.
Jan 26	Feb 9	N.P.Jouppi & S.J.E.Wilton, "Tradeoffs in Two-Level On-Chip Caching", Western Research Laboratory (Digital) Research Report 93/3.
Jan 26	Feb 11	S.Przybylski "SDRAMs Ready to Enter PC Mainstream" Microprocessor Report Vol 10, No 6 (May 6, 96).
Feb 29	Mar 2	D.Bhandarkar & D.W.Clark, "Performance from Architecture: Comparing a RISC and CISC with Similar Hardware Organization", ASPLOS 4, Palo Alto (April 91), 310-319.
Feb 29	Mar 4	J.E.Smith & S.Weiss, "PowerPC 601 and Alpha 21064: A Tale of Two RISCs", IEEE Computer, 27, 6 (June 94), 46-58.
Mar 2	Mar 9	HP Appendix D or Equivalent (x86 ISA)
Mar 9	Mar 16	M.Slater, "AMD's K5 Designed to Outrun Pentium", MR, 8, 14 (24 Oct 94).
Mar 9	Mar 16	L.Gwennap, "Intel's P6 Uses Decoupled Superscalar Design", MR, 9, 2 (19 Feb 95).
Mar 9	Mar 18	B.Case "New Instruction Sets Are Comming" Microprocessor Report Vol. 10 No. 10 (Aug. 5, 96).
Mar 9	Mar 18	W-M.W.Hwu et al., "Compiler Technology for Future Microprocessors", Proc IEEE, Vol. 83 No. 12 (December 1995), 1625-1640.
Mar 18	Mar 23	L.Gwennap, "Intel, HP Make EPIC Disclosure", Microprocessor Report Vol. 11 No. 14 (Oct. 27, 97).
Mar 18	Mar 23	L.Gwennap, "Merced Slips to Mid-2000", Microprocessor Report Vol. 12 No. 8 (Jun. 22, 98).
Mar 18	Mar 23	H.McGhan & M.O'Connor, "PicoJava: A Direct Execution Engine for Java Bytecode", IEEE Computer Vol. 31 No. 10 (Oct 98), 22-30.
Mar 18	Mar 25	D.Dobberpuhl, "The Design of a High Performance Low Power Microprocessor", Intl Symp Low Power Electronic Design, 1996, 11-16.
Mar 18	Mar 30	R.F.Sproull, I.E.Sutherland, C.E. Molnar, "Counterflow Pipeline Processor Architecture", Sun Microsystems Laboratories Technical Report, SMLI TR-94-25 (April 1994).