| Assigned | First Discussed | Reading
|
|---|
| 8 Jan | Jan 13-15 | HP 1.1-1.8. I will try to find
equivalent material in PH and HP-old.
|
| 15 Jan | 20 Jan | J.A.Fisher & B.R.Rau,
"Instruction Level Parallel Processing", Science, 253 (13
Sept 91), 1233-1241.
|
| 15 Jan | 22 Jan | J.E.Smith & G.S.Sohi, "The
Microarchitecture of Superscalar Processors", Proc. of the
IEEE, 83, 12 (Dec 95), 1609-1624.
|
| 15 Jan | 27 Jan | J.E.Smith & A.R.Pleszkun,
"Implementing Precise Interrupts in Pipelined Processors", IEEE
Trans. on Computers, 37, 5 (May 88), 562-573.
|
| 15 Jan | 29 Jan | L.Gwennap, "New Algorithm Improves
Branch Prediction", MR, 9, 4 (27 March 95).
|
| | S.Przybylski, "New DRAMs
Improve Bandwidth (Part 1)", MR, 7, 2 (15 Feb 93).
|
| | G.S.Sohi & M.Frenklin "High-Bandwidth Data Memory
Systems for Superscalar Processors" 53-62.
|
| | S.Przybylski "SDRAMs Ready to Enter PC
Mainstream" Microprocessor Report Vol 10, No 6 (May 6, 96).
|
| | N.P.Jouppi & S.J.E.Wilton "Tradeoffs in Two-Level
On-Chip Caching" (Nov 11, 93).
|
| | J.E.Smith & S.Weiss "PowerPC 601 and Alpha 21064:
A Tale of Two RISCs" Computer (June 94) 46-58.
|
| | T.R.Halfhill "Beyond Pentium II" Byte
(Dec. 97) 80-86.
|
| | B.Case "New Instruction Sets Are Comming"
Microprocessor Report Vol. 10 No. 10 (Aug. 5, 96).
|
| | D.BhanDarkar & D.W.Clark "Performance from
Architecture: Comparing a RISC and a Cisc with similar Hardware
Orginization" ASPLOS IV Proceedings (Apr, 91) 310-319.
|