Goto CS418 Home Page

CPSC 418: Readings

Required Articles

Articles are handed out during class -- one copy per student.

The following abbreviations are used:

Handed Out First Discussed Article
9 Jan28 Jan D.Bhandarkar & D.W.Clark, "Performance from Architecture: Comparing a RISC and CISC with Similar Hardware Organization", ASPLOS 4, Palo Alto (April 91), 310-319.
14 Jan30 Jan J.E.Smith & S.Weiss, "PowerPC 601 and Alpha 21064: A Tale of Two RISCs", IEEE Computer, 27, 6 (June 94), 46-58.
28 Jan 4 Feb J.A.Fisher & B.R.Rau, "Instruction Level Parallel Processing", Science, 253 (13 Sept 91), 1233-1241.
6 Feb J.E.Smith & G.S.Sohi, "The Microarchitecture of Superscalar Processors", Proc. of the IEEE, 83, 12 (Dec 95), 1609-1624.
25 Feb J.E.Smith & A.R.Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", IEEE Trans. on Computers, 37, 5 (May 88), 562-573.
25 Feb 27 Feb L.Gwennap, "New Algorithm Improves Branch Prediction", MR, 9, 4 (27 March 95).
4 Mar L.Gwennap, "Digital Leads the Pack with 21164", MR, 8, 12 (12 Sept 94).
L.Gwennap, "Digital 21264 Sets New Standard", MR (28 Oct 96).
not done B.Case, "New Instruction Sets Are Coming", MR (5 Aug 96).
13 Mar B.Case "Updated SPEC Benchmarks Released", MR, 6, 12 (16 Sept 92).
B.Case, "SPEC95 Retires SPEC92", MR, 9, 11 (21 Aug 95).
L.Gwennap, "Intel Updates Its iCOMP Index", MR (8 July 96).
18 Mar 20 Mar S.Przybylski, "New DRAMs Improve Bandwidth (Part 1)", MR, 7, 2 (15 Feb 93).
S.Przybylski, "DRAMs for New Memory Systems (Part 2)", MR, 7, 3 (8 March 93).
S.Przybylski, "DRAMs for New Memory Systems (Part 3)", MR, 7, 4 (29 March 93).
27 Mar G.S.Sohi & M.Franklin, "High-Bandwidth Data Memory Systems for Superscalar Processors", ASPLOS 4, Palo Alto (April 91), p.53-62.
27 Mar N.P.Jouppi & S.J.E.Wilton, "Tradeoffs in Two-Level On-Chip Caching", Western Research Laboratory (Digital) Research Report 93/3.
03 Apr B.Case, "Intel Reveals Pentium Implementation Details", MR, 7, 4 (29 March 93).
L.Gwennap, "Cyrix Describes Pentium Competitor", MR, 7, 14 (25 Oct 93).
L.Gwennap, "Intel's P6 Uses Decoupled Superscalar Design", MR, 9, 2 (19 Feb 95).
not done M.Rosenblum et.al., "The Impact of Architectural Trends on Operating System Performance", Proc. Symposium on Operating System Principles (Dec 95), 285-298.
not done D.M.Tullsen, S.J.Eggers, & H.M.Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism", ISCA 22, Santa Margherita Ligure Italy (June 95).

Supplemental Readings from Texts

The texts are:

Topic Text Chapters Notes
Performance HP 2.1, 2.2, 2.5 up to "Choosing Programs to Evaluate Performance" from 2.2
PH 2.1 - 2.4, 2.6 - 2.8
Cost-Performance HP 2.4, 2.6
ISA Design HP 3 only "how architects can help compilers" from 3.7
FR 1.3 - 1.5 ignore compiler parts
Example ISAs HP 4.1, 4.2, 4.4 - 4.9 DLX is very similar to MIPS, we will study VAX only briefly
FR 2.1 - 2.3, 2.7 we will not directly study FR's ISA
PH 3 MIPS: our basic RISC ISA
App. E VAX
Basic Pipelining PH 3
HP 6.1 - 6.5, 6.10 - 6.12
Instruction Parallelism HP 6.8 good supplement to Fisher & Rau
Dynamic scheduling HP 6.6 out-of-order completion
6.7 out-of-order issue
Cost HP 2.3
Benchmarking HP 2.2 Last part of section
PH 2.5, 2.6
Memory Hierarchy HP 8.1 - 8.2, 8.9 - 8.11 basic hierarchy principles
8.3 basic cache principles
8.4 increasing memory bandwidth
8.8 improving cache performance
PH 7.1 - 7.2, 7.4 - 7.7 basic hierarchy & cache principles + improving memory bandwidth

Other Readings

Goto CS418 Home Page
Last modified: Jan 97