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CpSc-418\hfill{\bf\LARGE Midterm Exam}\hfill{March~6, 1997}\\
Maximum Marks: 100\hfill{Time: 80 minutes}\\[1.0cm]
\begin{description}

  \item{\em 1.~Factors affecting Performance (18 points)}\\
Given a user's program (written in a high level language like C), most
computer architects will agree that the appropriate way to measure a
processor's performance on that program is given by the following
equation:

\[
	\mbox{\em performance} = \frac{machine\ instr.}{program} \times
		\frac{cycles}{machine\ instr.} \times
		\frac{time}{cycle}
\]

    \begin{description}

      \item{\em a.} For each of the three terms, explain
	how ISA choices can affect that term.

      \item{\em b.} For each of the three terms, give a
	factor other than ISA which has an affect (ie three different
	factors).\\[0.75cm]

    \end{description}


  \item{\em 2.~Reducing the Instruction Set (24 points)}\\
Discuss the ways in which each of the instruction types given below
might complicate a RISC style pipelined processor (a paragraph per
part).  

    \begin{description}
      \item{\em a.}
	Autoincrement addressing for loads/stores
      \item{\em b.}
	Absolute addressing for branch targets
      \item{\em c.}
	String Move
    \end{description}

Some issues you may wish to consider include
\begin{itemize}
\item instruction encoding
\item interrupt handling
\item frequency that the instruction type might occur
\item ease with which the
instruction type can be synthesized from simpler instructions
\item hazards introduced by pipelining that instruction with other
instructions.
\end{itemize}

\newpage

  \item{\em 3.~RISC and CISC.  What a lousy names. (12 points)}\\
Following Smith \& Weiss, we compared the Alpha and PowerPC architectures.
The article began with the following quote by P.Hester:

{\small
\begin{quote}
At this point many RISC purists will undoubtedly claim that this is
not a RISC design... This second generation RISC design, representing
a reasonable melding of RISC and CISC concepts, is likely to be the
direction of many future RISC designs.
\end{quote}}

Despite this ``melding'', I would claim that the PowerPC is far more
similar to the Alpha (a very RISC processor) than it is to the VAX
(the canonical CISC processor).

State the major differences between RISC and CISC architectures.  Then
support or refute my statement (NOT P.Hester's) by explaining where
the PowerPC lies with respect to these differences.\\[0.75cm]


  \item{\em 4.~Faster Processors (25 points)}\\
What problems that occur in modern superscalar and/or superpipelined
processors do each of the following techniques/units solve?  Explain
briefly (1-3 sentences) how the unit/technique solves the problem.

    \begin{description}
      \item{\em a.}
	ROB
      \item{\em b.}
	multiple integer ALUs
      \item{\em c.}
	Tomasulo's algorithm and its derivatives
      \item{\em d.}
	separate ALU and MEM pipeline stages
      \item{\em e.}
	explicitly set instead of implicitly set condition codes\\[0.75cm]
    \end{description}


  \item{\em 5.~Instruction Level Parallelism (15 points)}
    \begin{description}

      \item{\em a.} Define a ``sequential execution
	architecture''.

      \item{\em b.} How do the dataflow and VLIW
	architectures differ from the sequential execution
	architecture?

      \item{\em c.} Give one example of how the MIPS R2000
	ISA fails to support the sequential execution architecture
	assumption, and why this failure is a problem.

    \end{description}

\newpage

  \item{\em 6.~All these funky units\ldots (18 points)}\\
The figure on the following page is a functional unit diagram of the
Alpha 21264 microprocessor (from ``Digital 21264 Sets New Standard'',
Linley Gwennap, {\em Microprocessor Report}, October 28, 1996, p.11 and
provided in the last article package).  In studying advanced
processors, we have divided the pipeline into 5 major stages:

\begin{description}
\item{1. Fetch} 
\item{2. Dispatch}
\item{3. Issue} 
\item{4. Execute}
\item{5. Commit} 
\end{description}

In your exam booklet, make a table with three columns.  On the left
will be the letters corresponding to the functional units listed
below.  Beside each letter (in the middle column) will be the
number(s) of the stage(s) in which that unit is used.  On the right
will be short explanations of why that unit is used in those stage(s)
(1 sentence per stage in which the unit is used).

For example, if the branch predictor unit was given letter ``z'',
your exam booklet should have the following line:
\begin{center}\begin{tabular}{|c|c|l|}
	\hline
    unit & stage(s) & why? \\ \hline
	z & 1 & to determine which instructions to fetch \\
	  &   & despite conditional branches \\ \hline
\end{tabular}\end{center}

    \begin{description}
      \item{a.~Instruction Cache \& TLB}
      \item{b.~Retire Unit / Decode \& Rename Regs}
      \item{c.~Integer / FP Instruction Queues}
      \item{d.~Addr ALU / Int Unit / FP Add\ldots / FP Mul}
      \item{e.~Int. Regs / FP Regs}
      \item{f.~Data Cache \& TLB}
      \item{g.~L2 Cache \& Bus Interface}
    \end{description}

{\em For this figure, see the article (handed out in class) listed above}

\end{description}
\end{document}
