CPSC 418: Solution 6

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Problem 1

Most significant disadvantages to segmented memory systems:

Dynamic Growth: Each segment has a fixed base address. The maximum size of a segment is the amount of space betweeen its base address and the base address of the adjacent segment in the direction the segment will grow. (Note: Heap/Stack are bit more complicated than that.) When a segment needs to grow beyond its maximum size, the operating system must either kill the process or perform memory compaction ("crunching").
Inefficient use of physical memory: The operating system must allocate each segment a contiguous chunk of memory at least as large as the maximum amount of memory the segment will require. This leads to holes between chunks that cannot be used because they are smaller than any segment. Also, if a segment does not use all of the memory allocated for it, that memory goes unused.

Problem 2

 
Given four segments: Absolute, Program, Data, Stack
 
   switch segment { 
   case ABSOLUTE: 
       physical_addr = absolute_base + index; 
       break; 
   case PROGRAM: 
       physical_addr = program_base + index; 
       break; 
   case DATA: 
       physical_addr = data_base + index; 
       break; 
   case STACK: 
       physical_addr = stack_base + index; 
       break; }

Problem 3

Hardware resources required in a segmented memory system:

Two registers for each segment that a process has - one register is for the base and the other for the maximum size
Comparator for protection faults
Adder for physical address calculation
one copy of each segment register per interrupt level (if saved registers in hardware)

Operating system has to:

Calculate base address for each segment when it is created
Perform compaction ("crunching")
Save segment registers on stack for context switch (if not saved in hardware)
Supervisor-mode instructions that modify max-size registers

Problem 4

(Part 4a)

If a Brainiac does three times as much work per clock cycle as a Speeed-demon, then it can achieve equivalent performance.

(Part 4b)

Intel P6 is generally a Speed-demon.

200 MHz (speed of P6) is on the upper range of processor speeds
RISC instructions that are generated from x86 instructions are very simple

Problem 5

(Part 5a)

Power2 has the following instructions which DEC Alpha does not:

FMA instruction (Floating Point Multiply Add)
Floating-point square root
BCT (Branch Count)
Quad word Load/Store
Load/Store with update

(Part 5b)

The BCT instruction leads to extra count register in the Power2.
OR
The FMA and square-root instructions lead to larger floating point unit in the Power2.

NOTE: Simply saying that the more complex instructions in Power2 leads to more transistors is not sufficient.

(Part 5c)

In order for Power2 programs to utilize the performance features of the Power2 architecture, Power2 compilers must recognize cases where they can use the more complex instructions. In general this requires more sophisticated compilers than with simpler instruction sets.

Simple answer: compilers must recognize when they can use the more complex instructions.

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Last modified: 26 Feb 96