CPSC 418 --- Advanced Computer Architecture --- Spring 1996
Homework 08 --- Due 12 Mar
Problem 1 (6 Points)
Parts (a) and (b) both refer to an instruction cache with:
- word addressing
- 64 words
- 4 words per block
- least-recently-used replacement scheme
1(a) (3 Points)
Use a picture and (words and/or pseudo-code) to describe how the above
cache with two-way set associativivity detects a cache miss
and handles the subsequent fill.
1(b) (3 Points)
Use a picture and (words and/or pseudo-code) to describe how the above
cache with four-way set associativivity detects a cache miss
and handles the subsequent fill.
Problem 2 (8 Points)
Given a two-level memory system (split instruction/data L1-caches and
main memory):
L1 data-cache:
- 95% hit rate
- 30% of cache accesses are writes
- at any point in time, 25% of blocks in cache have been modified
- 8 words per block
- 1 cycle access time
- Transfer rate between registers and L1-cache: 1 word/cycle
- not-last-used replacement scheme
Main memory:
- 20 cycle access time
- Transfer rate between L1-cache and main memory: 8 words/cycle
2(a) (4 Points)
Calculate the average data access time if the cache uses write-through with
no-write-allocate on write miss.
2(b) (4 Points)
Calculate the average access time if the cache uses write-back with
write-allocate on write miss.
Problem 3 (5 Points)
3(a) (3 Points)
What are the tradeoffs in using virtual addresses or physical
addresses for caches?
3(b) (2 Points)
Would you use virtual or physical addresses for a cache?
Justify your answer.
Problem 4 (1 Point)
How much time did you spend total on the assignment and on each of
these problems? Which problems were useful or useless? How well
did the lectures and text book prepare you for this homework?
Which concepts needed better explanation?
Last modified: 05 Mar 96
