CPSC 418: HW-02 Clarification 2
Gate Delays and Logic Optimization
A student sent email asking about the purpose in comparing increase in
clock speed vs. decrease in feature size for microprocessors.
The purpose of this comparison is to detect circuit level (i.e. below
microarchitectural) changes. For example, doing logic optimization
(Boolean equations, de Morgan's laws, etc) to reduce the number of
gates that a signal has to pass through within one clock cycle. If
the number is less than one, then the company must have found a
tradeoff where they would increase the number of gate delays in a
clock cycle in order to gain more performance somewhere else.
Remember: for a given Boolean function, to increase speed (decrease gate
delays) you usually have to increase the number of gates. This changes
a long narrow circuit (small and slow) into one that is short and
wide.
For example:
p = (a AND b AND c) OR (a AND b AND d) OR (a AND b AND e)
q = (g AND c) OR (g AND d) OR h
Can be written as:
p = (y AND z) OR (y AND e)
q = (g AND z) OR h
y = a AND b
z = c OR d
This transformation reduced the size of the circuit from 12 gates
to 7, but increased the number of gate delays from 2 to 3.
Microprocessor Comparison
For problem 2 you should compare 10 different computers or
microprocessors, not ten architectures. Each row in Handout 5
is one microprocessor. Handout 5 can be your primary source of
information, but it would be good if you find additional sources of
information also.
Last modified: 15 Jan 96
